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| MC14001UB, MC14011UB UB-Suffix Series CMOS Gates The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non-buffered functions. Features http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 P SUFFIX CASE 646 1 MC140xxUBCP AWLYYWW * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Linear and Oscillator Applications * Capable of Driving Two Low-Power TTL Loads or One * * * Low-Power Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs Pin-for-Pin Replacements for Corresponding CD4000 Series UB Suffix Devices Pb-Free Packages are Available* 14 SOIC-14 D SUFFIX CASE 751A 1 140xxU AWLYWW MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C xx A WL, L YY, Y WW, W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2005 1 February, 2005 - Rev. 5 Publication Order Number: MC14001UB/D MC14001UB, MC14011UB LOGIC DIAGRAMS MC14001UB Quad 2-Input NOR Gate 1 2 5 6 8 9 12 13 3 4 10 11 1 2 5 6 8 9 12 13 MC14011UB Quad 2-Input NAND Gate 3 4 10 11 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES PIN ASSIGNMENTS MC14001UB Quad 2-Input NOR Gate IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C MC14011UB Quad 2-Input NAND Gate IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C http://onsemi.com 2 MC14001UB, MC14011UB IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I III I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I III I I I I I I I I I III II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 15 - - 55_C 25_C 125_C MinIII Max - - - 0.05 0.05 0.05 - - - Min - - - Typ (Note 2) 0 0 0 Max Min - - - Max Unit Output Voltage Vin = VDD or 0 Vin = 0 or VDD "0" Level VOL 0.05 0.05 0.05 - - - 0.05 0.05 0.05 - - - Vdc "1" Level VOH 4.95 9.95 14.95 - - - 4.95 9.95 14.95 - - - 5.0 10 15 4.95 9.95 14.95 - - - Vdc Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) "0" Level VIL Vdc 1.0 2.0 2.5 - - - - - - - - - - 2.25 4.50 6.75 2.75 5.50 8.25 1.0 2.0 2.5 - - - - - - - - - - 1.0 2.0 2.5 - - - - - - - - - - "1" Level IIH 4.0 8.0 12.5 4.0 8.0 12.5 4.0 8.0 12.5 Vdc Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH mAdc Source - 1.2 - 0.25 - 0.62 - 1.8 0.64 1.6 4.2 - - - - - - 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 - - - - - - 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8 - 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 - - - - - Sink IOL mAdc Input Current Iin 0.1 - 0.00001 5.0 0.1 7.5 1.0 - mAdc pF Input Capacitance (Vin = 0) Cin Quiescent Current (Per Package) IDD 5.0 10 15 5.0 10 15 0.25 0.5 1.0 0.0005 0.0010 0.0015 0.25 0.5 1.0 7.5 15 30 mAdc Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Gate CL = 50 pF) IT IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.8 mA/kHz) f + IDD/N mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mH (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. II I I I I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min Typ (Note 6) 180 90 65 100 50 40 90 50 40 Max Unit ns Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns - - - - - - - - - 360 180 130 200 100 80 180 100 80 Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 30 ns tPLH, tPHL = (0.66 ns/pF) CL + 22 ns tPLH, tPHL = (0.50 ns/pF) CL + 15 ns tPLH, tPHL ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. http://onsemi.com 3 MC14001UB, MC14011UB ORDERING INFORMATION Device MC14001UBCP MC14001UBCPG MC14001UBD MC14001UBDG MC14001UBDR2 MC14001UBDR2G Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 55 Units / Rail 55 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel MC14011UBCP MC14011UBCPG MC14011UBD MC14011UBDG MC14011UBDR2 MC14011UBDR2G PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) 500 Units / Rail 500 Units / Rail 55 Units / Rail 55 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 20 ns 14 PULSE GENERATOR INPUT * 7 VSS tTHL VDD OUTPUT tPHL CL OUTPUT INVERTING 90% 50% 10% tTLH INPUT 90% 50% 10% 20 ns VDD 0V tPLH VOH VOL *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. Figure 1. Switching Time Test Circuit and Waveforms http://onsemi.com 4 MC14001UB, MC14011UB MC14001UB CIRCUIT SCHEMATIC VDD 14 MC14011UB CIRCUIT SCHEMATIC (1/4 of Device Shown) 14 VDD 8 9 3 10 1 2 3, 4, 10, 11 1, 6, 8, 13 2, 5, 9, 12 6 5 13 12 7 VSS 4 7 VSS 11 16 Vout , OUTPUT VOLTAGE (Vdc) 14 12 10 8.0 6.0 4.0 2.0 0 0 Vout , OUTPUT VOLTAGE (Vdc) I D, DRAIN CURRENT (mAdc) VDD = 15 Vdc TA = +25C Unused input connected to VSS. a One input only 10 Vdc b Both inputs 8.0 b 5.0 Vdc b ba a a 6.0 15 Vdc 10 Vdc 4.0 2.0 16 14 12 10 8.0 VDD = 15 Vdc Unused input connected to b VSS. a 10 Vdc a TA = +125C b TA = -55C a b 6.0 4.0 2.0 0 0 5.0 Vdc ab 0 2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc) 2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc) Figure 2. Typical Voltage and Current Transfer Characteristics Figure 3. Typical Voltage Transfer Characteristics versus Temperature 0 -2.0 VGS = -5.0 Vdc a TA = -55C b TA = +25C c TA = +125C c -10 Vdc -8.0 b c b I D, DRAIN CURRENT (mAdc) a 10 a b c a b c 15 Vdc VGS = 10 Vdc I D, DRAIN CURRENT (mAdc) 8.0 -4.0 6.0 -6.0 4.0 a b c a TA = -55C b TA = +25C c TA = +125C c b a a -2.0 -15 Vdc 2.0 0 5.0 Vdc -10 -10 -8.0 -6.0 -4.0 VDS, DRAIN VOLTAGE (Vdc) 0 0 2.0 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 10 Figure 4. Typical Output Source Characteristics Figure 5. Typical Output Sink Characteristics http://onsemi.com 5 MC14001UB, MC14011UB PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 14 8 B 1 7 A F N -T- SEATING PLANE L C K H G D 14 PL 0.13 (0.005) M J M DIM A B C D F G H J K L M N http://onsemi.com 6 MC14001UB, MC14011UB PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE G -A- 14 8 -B- P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R http://onsemi.com 7 MC14001UB, MC14011UB ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC14001UB/D |
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